1. Technical Field
The present application generally relates to a semiconductor device. More specifically, the present application relates to a semiconductor device including a memory cell.
2. Related Art
A flash memory device having a 3-dimensional structure including a vertical channel applies a ground voltage to word lines to perform an erase operation of a memory cell, and select lines and dummy word lines maintain floating states. When a pipe gate line is added, the pipe gate line also maintains a floating state. When a high erase voltage is applied to the vertical channel, voltages of the select lines and the dummy word lines in a floating state are increased by a capacitor coupling phenomenon, and a vertical electric field is formed. Thus, electrons are trapped in a charge trap layer of the memory cell.
Since the voltage of the select line is highly increased and is increased more, a threshold voltage may be abnormally increased. As a result, an error may be generated.